### Q Series Motion Controller (Q***DCPU)

Device | Bit Address | Word Address | 32 bits | Notes
--- | --- | --- | --- | ---
Input Relay | X0000-X1FFF | X0000-X1FF0 |  |
Output Relay | Y0000-Y1FFF | Y0000-Y1FF0 |
Internal Relay | M00000-M12287 | M00000-M12272 |
Special Relay | SM0000-SM2255 | SM0000-SM2240 |
Annunciator | F00000-F02047 | F00000-F02032 |
Link Relay | B0000-B1FFF | B0000-B1FF0 |
Data Register | ------ | D0000000-D0008191 |
Special Register | ------ | SD0000-SD2255 |
Link Register | ------ | W0000-W1FFF |
Common device for Multiple CPU *1 | ------ | U3E0-10000 - U3E0-24335 |
------ | U3E1-10000 - U3E1-24335 |
------ | U3E2-10000 - U3E2-24335 |
------ | U3E3-10000 - U3E3-24335 |
Motion Register (#) *2 | ------ | %MR00000-%MR12287*3 |

*1For the Multi CPU System configuration, the available points should be as follows:

2 CPUs: 14k points or less

3 CPUs: 13k points or less

4 CPUs: 12k points or less

*2No. 2 to No. 4 can be allocated to the motion CPU.

*3Device name with motion CPU is #.

NOTE

- The notation of addresses differs depending on a selected Unit No.
  <Ex.>When 0 is selected for Unit No.,

  <Ex.>When 1 is selected for Unit No.,

- Please refer to the precautions on manual notation for icons in the table.
  Supported Devices Symbol and Terms